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r03ds0052ej0100 rev.1.00 page 1 of 13 dec 19, 2011 preliminary datasheet R2A20133DSP critical conduction mode pfc control ic description the r2a20133d controls a boost converter to provide an active power factor correction. the r2a20133d adopts critical conduction mode for power factor correction and realizes high ef ficiency and a low switching noise by zero current switching. because the zero current is detected by using the gnd current, the zcd auxilia ry winding is unnecessary. the feedback loop open detection, two mode overvoltage pr otection, overcurrent protection are built in the r2a20133d, and can constitute a power supply system of high reliability with few external parts. features ? absolute maximum ratings ? supply voltage vcc: 24 v ? operating junction temperature tjopr: ?40 to +150c ? electrical characteristics ? uvlo operation start voltage vh: 9.5 v ? 0.7 v ? uvlo operation shutdown voltage vl: 8.5 v ? 0.4 v ? uvlo hysteresis voltage hysuvl: 1.0 v ? 0.4 v ? functions ? boost converter control with critical conduction mode ? two mode overvoltage protection and ovp2 mode 1: dynamic ovp corresponding to a voltage rise by load change mode 2: static ovp corresponding to overvoltage in stable. ovp2: ovp2 senses the pfc output voltage by independence pin. ? feedback loop, open detection ? overcurrent protection ? dynamic uvp corresponding to a voltage fall by load change ? frequency limiter, adjustable ? zero current detect (zcd) delay time, adjustable ? cs pin's open detection ? package lineup: pb-free sop-8 (jedec) ordering information part no. package name package code package abbreviation taping abbreviation (quantity) R2A20133DSP#w5 ? prsp0008dj-a sp w (2,500 pcs/reel) r03ds0052ej0100 rev.1.00 dec 19, 2011
R2A20133DSP preliminary r03ds0052ej0100 rev.1.00 page 2 of 13 dec 19, 2011 pin arrangement (top view) fb 1 rt 2 comp 3 ovp2 vcc out gnd cs 4 8 7 6 5 pin functions pin no. pin name function 1 fb error amplifier input terminal 2 rt max-on time, zcd-delay and frequency limiter adjustment terminal 3 comp error amplifier output terminal 4 ovp2 over voltage detection terminal 5 cs zero current detection and overcurrent detection input terminal 6 gnd ground 7 out power mosfet drive terminal 8 vcc supply voltage terminal
R2A20133DSP preliminary r03ds0052ej0100 rev.1.00 page 3 of 13 dec 19, 2011 block diagram uvlo ovp & fb_low block fb gd disable (ovp & fb_low) on: 9.5v off: 8.5v vref: 5.02v ramp control logic block ovp2 cs 5 rt 2 vcc 8 out 7 gnd 6 fb 1 comp 3 ovp2 4 ?0.6v 60k vref 5p ? + ? + 3mv 72.5mv ocp comparator zcd comparator pwm comparator cs open comparator + ? 42a 1v 10p ? + vref erroramp 4.1v 2.51v (vfb) ? + comp discharge vfb 1.04v dynamic ovp dynamic uvp + ? vfb 0.92v + ?
R2A20133DSP preliminary r03ds0052ej0100 rev.1.00 page 4 of 13 dec 19, 2011 absolute maximum ratings (ta = 25c) item symbol ratings unit note supply voltage vcc ?0.3 to +24 v out terminal peak current ipk-snk-out ipk-src-out +0.9 ?0.5 a 3 out terminal dc current idc-snk-out idc-src-out +100 ?50 ma comp terminal current icomp +1 ?1 ma rt terminal current irt ?50 to ?2 ? a vt-group1 ?0.3 to vcc 4 terminal voltage vt-group2 ?0.3 to 5.3 v 5 cs terminal voltage vcs ?5 to +0.3 v power dissipation pt 0.68 w 6 operating junction temperatur e tj-opr ?40 to +150 c storage temperature tstg ?55 to +150 c notes: 1. rated voltages are with reference to the gnd terminal. 2. for rated currents, inflow to the ic is indicated by (+), and outflow by (?). 3. shows the transient current when driving a capacitive load. 4. this is the rated voltage for the following pins: out 5. this is the rated voltage for the following pins: fb, comp, ovp2, rt 6. ? ja = 120c/w this value is a thing mounting on 40 ? 40 ? 1.6 [mm], a glass epoxy bo ard of wiring density 10%.
R2A20133DSP preliminary r03ds0052ej0100 rev.1.00 page 5 of 13 dec 19, 2011 electrical characteristics (ta = 25c, vcc = 12 v, cs = 0.04 v, fb = 2 v, comp: open, ovp2 = 1 v, rrt = 200 k ? ) item symbol min typ max unit test conditions uvlo turn-on threshold vuvlh 8.8 9.5 10.2 v uvlo turn-off threshold vuvll 8.1 8.5 8.9 v uvlo hysteresis hysuvl 0.6 1.0 1.4 v standby current istby ? 100 200 ? a vcc = vuvlh ? 0.2 v supply operating current icc ? 1.8 2.6 ma feedback voltage vfb 2.472 2.510 2.548 v fb-comp short temperature stability dvfb ? ? 80 ? ppm/c ta = ?40 to +125c * 1 input bias current ifb ?0.40 ?0.15 ?0.05 ? a measured pin: fb open loop gain av ? 65 ? db * 1 upper clamp voltage vclamp-comp 3.75 4.10 4.35 v fb = 2.45 v comp: open low voltage vl-comp ? 0.1 0.3 v fb = 3.0 v comp: open source current1 isrc-comp1 ?13.5 ?10 ?6 ? a fb = 1.7 v comp = 2.5 v source current2 isrc-comp2 isrc-comp1 ?3.3 isrc-comp1 ?3.0 isrc-comp1 ?2.7 ? a fb = 1.5 v comp = 2.5 v sink current isnk-comp 6 10 13.5 ? a fb = 3.5 v comp = 2.5 v error amplifier transconductance gm 25 46 75 ? s fb = 2.45v ? 2.55 v comp = 2.5 v ramp offset voltage voff_ramp ? 1.0 ? v * 1 ramp amplitude dvramp 2.90 3.1 3.3 v * 2 rt voltage v-rt 2.5 2.6 2.7 v zcd delay time zcd-delay ? 0.87 ? ? s rrt = 200 k ? * 1 rt maximum frequency fmax ? 500 ? khz rrt = 200 k ? * 1 zcd threshold voltage vzcd 1 3 6 mv input bias current ics ?58 ?42 ?25 ? a vcs = 0 v zero current detector cs open detect threshold voltage vcs-open 45 72.5 130 mv restart restart time delay tstart 75 150 330 ? s fb = 2.0 v comp = 2.5 v notes: * 1 design spec * 2 dvramp = vclamp_comp ? voff_ramp
R2A20133DSP preliminary r03ds0052ej0100 rev.1.00 page 6 of 13 dec 19, 2011 electrical characteristics (cont.) (ta = 25c, vcc = 12 v, cs = 0.04 v, fb = 2 v, comp: open, ovp2 = 1 v, rrt = 200 k ? ) item symbol min typ max unit test conditions rise time tr-out ? 35 100 ns cl = 1000 pf tr 90% 10% fall time tf-out ? 35 100 ns cl = 1000 pf tf 90% 10% vol1-out ? 0.08 0.2 v isink = 20 ma out low voltage vol2-out ? 0.05 0.7 v vcc = 5 v, isink = 10 ma out out high voltage voh-out 11.5 11.8 ? v isource = ?20 ma over current protection ocp threshold voltage vocp ?0.63 ?0.6 ?0.57 v dynamic ovp threshold voltage vdovp ? vfb ? 1.040 ? v measure fb * 1 dynamic uvp threshold voltage vduvp ? vfb ? 0.920 ? v * 1 static ovp threshold voltage vsovp vfb ? 1.075 vfb ? 1.090 vfb ? 1.105 v static ovp hysteresis hys-sovp 50 100 150 mv fb low detect threshold voltage vfblow 0.25 0.3 0.35 v fb low detect hysteresis hysfblow 0.16 0.20 0.24 v ovp2 high threshold voltage vovp2-high vfb ? 1.18 vfb ? 1.20 vfb ? 1.22 v measure ovp2 ovp2 low threshold voltage vovp2-low 0.1 0.2 0.3 v over & under voltage protection ovp2 source current isrc-ovp2 ?0.40 ?0.15 ?0.05 ? a note: * 1 design spec
R2A20133DSP preliminary r03ds0052ej0100 rev.1.00 page 7 of 13 dec 19, 2011 waveforms 1. start-up out vref good (internal signal) comp fb 0.5v (vfblow + hysfblow) vcc 9.5v (vuvlh) 5.02v 3.6v vref (internal signal) 2. shut-down out normal operation 8.5v (vuvll) vcc
R2A20133DSP preliminary r03ds0052ej0100 rev.1.00 page 8 of 13 dec 19, 2011 3. gate drive output ramp (internal signal) 0v 0v out ramp+1v (internal signal) ramp (internal signal) ramp+1v (internal signal) comp il cs 0.87s (adjustable) 0a enlargement around zero-current detection comp out il cs
R2A20133DSP preliminary r03ds0052ej0100 rev.1.00 page 9 of 13 dec 19, 2011 4. overvoltage protection (sovp) fb out comp 100mv (hys-sovp) vfb 1.09v (vsovp) sovp_on (internal signal) 5. fb low detection fb out 0.3v (vfblow) 0.5v (vfblow + hysfblow) comp fb_low (internal signal)
R2A20133DSP preliminary r03ds0052ej0100 rev.1.00 page 10 of 13 dec 19, 2011 6. overcurrent protection (ocp) 0v ?0.6v comp cs il out ramp (internal signal) ramp+1v (internal signal) 7. frequency limiter tmin = zcd_delay + zcd_mask = 1/fmax mask mask 0a il out zcd_pulse (internal signal) zcd_mask (internal signal) 1.13s zcd_delay 0.87s (adjustable) mask
R2A20133DSP preliminary r03ds0052ej0100 rev.1.00 page 11 of 13 dec 19, 2011 8. overvoltage protection 2 (ovp2) ovp2 vfb 1.2v (vovp2-high) ovp2_high (internal signal) out 9. ovp2 low detection ovp2 out 0.2v (vovp2-low) comp ovp2_low (internal signal)
R2A20133DSP preliminary r03ds0052ej0100 rev.1.00 page 12 of 13 dec 19, 2011 system diagram pfc out (390v dc) to q1 gate 1 aux 0.022 0.047 200k 200k 180 1000p gnd l1 220 (450v) d1 + 6m vrb1 6m vrb2 cs 5 rt 2 vcc 8 out 7 gnd 6 fb 1 comp 3 ovp2 4 r2a20133d 1.0 from out q1 0.05 (5w)
R2A20133DSP preliminary r03ds0052ej0100 rev.1.00 page 13 of 13 dec 19, 2011 package dimensions note) 1. dimensions"*1 (nom)"and" *2" do not include mold flash. 2. dimension"*3"does not include trim offset. 0.10 1.27 0.56 5.84 6.20 0.410.35 4.98 max nom min 4.80 3.99 3.81 dimension in millimeters symbol reference 1.73 0.890.640.41 3.94 1.47 0.25 0.150.10 0.49 0.250.20 0.19 5.99 8 0 0.25 1.03 4.93 e h e l a d e a 2 a 1 b p b 1 c x y z l 1 c 1 previous code jeita package code renesas code prsp0008dj-a ? mass[typ.] 0.073g p-sop8-3.94x4.93-1.27 c terminal cross section (ni/pd/au plating) detail f l 5 8 4 f *1 *2 *3 mx 1 index mark s s y a d e z e l 1 a 1 b p b p h e
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